Welcome to Acta Armamentarii ! Today is

Acta Armamentarii ›› 2012, Vol. 33 ›› Issue (12): 1480-1484.doi: 10.3969/j.issn.1000-1093.2012.12.012

• Paper • Previous Articles     Next Articles

Hardware Architecture Design and Analysis of a Fiber Optic Bus Based on the RapidIO Protocol

QIAN Ying-qing, WANG Xiao-feng, LAO Li, XU Run-hua, JIANG Liang-hong   

  1. (School of Mechanical Engineering, Nanjing University of Science and Technology, Nanjing 210094, Jiangsu, China)
  • Received:2011-08-15 Revised:2011-08-15 Online:2014-01-09
  • Contact: QIAN Ying-qing E-mail:qyq218@sh163.net

Abstract: A fiber optic bus based on the RapidIO protocol was designed. The bus uses a star topology structure. It expanded the shortdistance electrical interconnection between node and switch board into a longdistance fiber optic interconnection through highbandwidth and antijamming fiber channel, and it employed the backplane cascaded method and fiber optic cascaded method to achieve the expansion of the bus node. The paper focused on the hardware architecture design of the node, switch board, and the I/O board. According to the RapidIO protocol,through analyzing the impact of the delay on the transmission performance, it proposed the design method of adopting transmission delay calculation to guarantee the transmission performance, and then calculated the ultimate length of the optical fiber. In the preliminary stage of engineering design, it tested the waveform parameters of serial RapidIO data through fiber optic transmitter and receiver circuit, and verified its performance.

CLC Number: